Low conductivity (low-k) dielectric material is used in the sandwich structure of next-generation semiconductor devices in order to reduce the RC time delay. While global flatness of wafer surface becomes critical for deep sub-micro semiconductor fabrication process, chemical-mechanical polishing (CMP) becomes one of the key technologies for planarization of wafer surface. This paper investigated the effect of the low-k material on the CMP of the SiO2 cap layer of such a sandwiched wafer. Two types of wafers, blanket wafer and wafer with circuit pattern, are designed and conducted to investigate the effects of the thickness of the low-k layer under different polishing pressures and velocities. Material removal rate (RR) and non-uniformity (NU) are used as indices of the CMP process performance. The results show that the RR and NU of wafers with low-k layer, either blanket or with circuit pattern, become better when the pressure or velocity increases. The thickness of the low-k layer, however, has only tiny effect on the RR and NU.