Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor. However, the integration also introduces a layer of complexity in the thermal design and management of microprocessors. As a direct result of functional integration, the power map on a microprocessor is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface has been shown to be invalid post Pentium II architecture. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work has been done which includes numerical analysis and thermal Based optimization of a typical package consisting of a non-uniformly powered die, heat spreader, TIM I &II and the base of the heat sink. In this paper, an analytical approach to temperature distribution of a first level package with a non-uniformly powered die is carried out for the first time. The analytical model for two layer bodies developed by Haji-Sheikh et al. is extended to this typical package which is a multilayer body. The solution is to begin by designating each surface heat flux as a volumetric heat source. An inverse methodology will be applied to solve the equations for various surfaces to calculate maximum junction temperature for given multilayer body. Finally validation of the analytical solution will be carried out using developed numerical model.
Development of an Analytical Model to a Temperature Distribution of First Level Package With a Non-Uniformly Powered Die
Kaisare, A, Agonafer, D, Haji-Sheikh, A, Chrysler, G, & Mahajan, R. "Development of an Analytical Model to a Temperature Distribution of First Level Package With a Non-Uniformly Powered Die." Proceedings of the ASME 2007 International Mechanical Engineering Congress and Exposition. Volume 5: Electronics and Photonics. Seattle, Washington, USA. November 11–15, 2007. pp. 443-449. ASME. https://doi.org/10.1115/IMECE2007-43736
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