With 3D system packaging, more chips will be stacked on top of each other and connected by through silicon vias (TSVs). TSVs enable not only miniaturization, but also high bandwidth, lower power consumption, heterogeneous integration and minimal interconnect latency. Due to the difference in the coefficient of thermal expansion (CTE) of various materials in 3D packaging systems, high thermomechanical stresses develop. Stress measurements near these TSVs and bump pads are important to help understand the evolution of die stresses associated with the packaging process. Depending on the package, the pitch of vias/bumps ranges from a few microns to a few tens of microns. Unlike currently-used piezoresistive doped Si sensors that require high-temperature processing, metal-based sensors use low-temperature standard cleanroom processes such as UV lithography and physical vapor deposition. In this paper, nichrome metallic sensors have been fabricated using standard cleanroom processes, and the gauge factor of the sensing material has been determined through tensile and compressive loadings. In parallel to the experiments, finite-element simulations have been carried out to assess the influence of sensors on local stress fields, and it is found that although the influence is minimal for micro-scale sensors, it is essential to account for such change in stress fields.
Strain Monitoring Near Through Silicon Vias Using Metal Piezoresistive Sensors
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Taylor, C, Liu, X, & Sitaraman, SK. "Strain Monitoring Near Through Silicon Vias Using Metal Piezoresistive Sensors." Proceedings of the ASME 2014 International Mechanical Engineering Congress and Exposition. Volume 10: Micro- and Nano-Systems Engineering and Packaging. Montreal, Quebec, Canada. November 14–20, 2014. V010T13A042. ASME. https://doi.org/10.1115/IMECE2014-40041
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